 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| FEATURES LTC4267 Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator DESCRIPTIO The LTC(R)4267 combines an IEEE 802.3af compliant Powered Device (PD) interface with a current mode switching regulator, providing a complete power solution for PD applications. The LTC4267 integrates the 25k signature resistor, classification current source, thermal overload protection, signature disable and power good signal along with an undervoltage lockout optimized for use with the IEEErequired diode bridge. The precision dual level input current limit allows the LTC4267 to charge large load capacitors and interface with legacy PoE systems. The current mode switching regulator is designed for driving a 6V rated N-channel MOSFET and features programmable slope compensation, soft-start, and constant frequency operation, minimizing noise even with light loads. The LTC4267 includes an onboard error amplifier and voltage reference allowing use in both isolated and nonisolated configurations. The LTC4267 is available in space saving, low profile 16-pin SSOP or DFN packages. Complete Power Interface Port for IEEE 802(R).3af Powered Device (PD) Onboard 100V, 400mA UVLO Switch Precision Dual Level Inrush Current Limit Integrated Current Mode Switching Regulator Onboard 25k Signature Resistor with Disable Programmable Classification Current (Class 0-4) Thermal Overload Protection Power Good Signal Integrated Error Amplifier and Voltage Reference Low Profile 16-Pin SSOP and 3mm x 5mm DFN Packages APPLICATIO S IP Phone Power Management Wireless Access Points Security Cameras Power over Ethernet , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc. TYPICAL APPLICATIO Class 2 PD with 3.3V Isolated Power Supply PA1133 10k -48V FROM DATA PAIR SBM1040 3.3V 1.5A + HD01 VPORTP PVCC - SMAJ58A 0.1F + PVCC 4.7F + PWRGD LTC4267 NGATE SENSE RCLASS ITH/RUN VFB SIGDISA VPORTN PGND POUT 5F MIN 10k PVCC Si3440 0.1 470 -48V FROM SPARE PAIR + HD01 - RCLASS 68.1 1% 6.8k 22nF 100k BA5516 PS2911 U * U U 320F * CHASSIS TLV431 60.4k 4267 TA01 4267f 1 LTC4267 ABSOLUTE (Note 1) AXI U RATI GS SENSE to PGND Voltage .............................. -0.3V to 1V NGATE Peak Output Current (<10s) ..........................1A Operating Ambient Temperature Range LTC4267C ................................................ 0C to 70C LTC4267I .............................................-40C to 85C Junction Temperature GN Package ...................................................... 150C DHC Package .................................................... 125C Storage Temperature Range...................-65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C VPORTN with Respect to VPORTP Voltage ... 0.3V to -100V POUT, SIGDISA, PWRGD Voltage..................... VPORTN + 100V to VPORTN -0.3V PVCC to PGND Voltage (Note 2) Low Impedance Source ........................... -0.3V to 8V Current Fed .......................................... 5mA into PVCC RCLASS Voltage .................VPORTN + 7V to VPORTN - 0.3V PWRGD Current .....................................................10mA RCLASS Current.....................................................100mA NGATE to PGND Voltage ...........................-0.3V to PVCC VFB, ITH/RUN to PGND Voltages ................ -0.3V to 3.5V PACKAGE/ORDER I FOR ATIO TOP VIEW ITH/RUN PGND NGATE PVCC RCLASS NC VPORTN NC 1 2 3 4 5 6 7 8 17 16 VFB 15 PGND 14 SENSE 13 VPORTP 12 SIGDISA 11 PWRGD 10 POUT 9 NC ORDER PART NUMBER LTC4267CDHC LTC4267IDHC DFN PART* MARKING 4267 DHC16 PACKAGE 16-LEAD (3mm x 5mm) PLASTIC DFN TJMAX = 125C, JA = 43.5C/W EXPOSED PAD (PIN 17) MUST BE SOLDERED TO ELECTRICALLY ISOLATED PCB HEAT SINK Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS SYMBOL VPORTN PARAMETER Supply Voltage Maximum Operating Voltage Signature Range Classification Range UVLO Turn-On Voltage UVLO Turn-Off Voltage PVCC Turn-On Voltage PVCC Turn-Off Voltage PVCC Hysteresis PVCC Shunt Regulator Voltage The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS Voltage with Respect to VPORTP Pin (Notes 4, 5, 6) VTURNON VTURNOFF VHYST VCLAMP1mA Voltage with Respect to PGND Voltage with Respect to PGND VTURNON - VTURNOFF IPVCC = 1mA, VITH/RUN = 0V, Voltage with Respect to PGND 2 U U W WW U W TOP VIEW PGND 1 ITH/RUN 2 NGATE 3 PVCC 4 RCLASS 5 NC 6 VPORTN 7 PGND 8 16 PGND 15 VFB 14 SENSE 13 VPORTP 12 SIGDISA 11 PWRGD 10 POUT 9 PGND ORDER PART NUMBER LTC4267CGN LTC4267IGN GN PART MARKING 4267 4267I GN PACKAGE 16-LEAD NARROW PLASTIC SSOP TJMAX = 150C, JA = 90C/W MIN TYP MAX -57 -9.5 -21 -37.2 -31.5 9.2 6.8 10.3 UNITS V V V V V V V V V 4267f -1.5 -12.5 -34.8 -29.3 7.8 4.6 1.5 8.3 -36.0 -30.5 8.7 5.7 3.0 9.4 LTC4267 The denotes ELECTRICAL CHARACTERISTICS25C. (Note 3) the specifications which apply over the full operating temperature range, otherwise specifications are at T = A SYMBOL VMARGIN IVPORTN_ON IPVCC_ON PARAMETER VCLAMP1mA - VTURNON Margin VPORTN Supply Current when ON PVCC Supply Current Normal Operation Start-Up CONDITIONS MIN 0.05 TYP 0.6 MAX 3 UNITS V mA A A mA % k k IVPORTN_CLASS VPORTN Supply Current During Classification ICLASS Current Accuracy During Classification RSIGNATURE Signature Resistance RINVALID Invalid Signature Resistance VPORTN = -48V, POUT, PWRGD, SIGDISA Floating (Note 7) VITH/RUN - PGND = 1.3V PVCC - PGND = VTURNON - 100mV VPORTN = -17.5V, POUT Tied to VPORTP, RCLASS, SIGDISA Floating (Note 8) 10mA < ICLASS < 40mA, -12.5V VPORTN -21V (Notes 9, 10) -1.5V VPORTN - 9.5V, POUT Tied to VPORTP, IEEE 802.3af 2-Point Measurement (Notes 4, 5) -1.5V VPORTN - 9.5V, SIGDISA and POUT Tied to VPORTP, IEEE 802.3af 2-Point Measurement (Notes 4, 5) With Respect to VPORTN High Level Invalidates Signature (Note 11) With Respect to VPORTN Low Level Enables Signature With Respect to VPORTN I = 1mA VPORTN = -48V, PWRGD Referenced to VPORTN VPORTN = -48V, Voltage between VPORTN and POUT POUT Falling POUT Rising VPORTN = 0V, PWRGD FET Off, VPWRGD = 57V I = 350mA, VPORTN = -48V, Measured from VPORTN to POUT (Note 10) PVCC - PGND = VTURNON + 100mV VITH/RUN - PGND = 0V, PVCC - PGND = 8V Referenced to PGND, PVCC - PGND = 8V (Note 12) PVCC - PGND = 8V (Note 12) ITH/RUN Pin Load = 5A (Note 12) VTURNOFF < PVCC < VCLAMP (Note 12) ITH/RUN Sinking 5A, PVCC - PGND = 8V (Note 12) ITH/RUN Sourcing 5A, PVCC - PGND = 8V (Note 12) VPORTN = 0V, Power MOSFET Off, POUT = 57V (Note 13) VPORTN = -48V, POUT = -43V (Note 14, 15) 0C TA 70C -40C TA 85C VPORTN = -48V, POUT = -43V (Note 14, 15) VITH/RUN - PGND = 1.3V, PVCC - PGND = 8V VITH/RUN - PGND = 1.3V, VFB - PGND = 0.8V, PVCC - PGND = 8V VITH/RUN - PGND = 1.3V, VFB - PGND = 0.8V, PVCC - PGND = 8V 0.35 240 40 0.5 350 90 0.65 3.5 23.25 9 26.00 11.8 VIH VIL RINPUT VPG_OUT Signature Disable High Level Input Voltage Signature Disable Low Level Input Voltage Signature Disable, Input Resistance Power Good Output Low Voltage Power Good Trip Point 3 57 0.45 V V k V 100 0.5 VPG _FALL VPG_RISE IPG_LEAK RON VITHSHDN ITHSTART VFB IFB gm VO(LINE) VO(LOAD) IPOUT_LEAK ILIM_HI Power Good Leakage Current On-Resistance Shutdown Threshold (at ITH/RUN) Start-Up Current Source at ITH/RUN Regulated Feedback Voltage VFB Input Current Error Amplifier Transconductance Output Voltage Line Regulation Output Voltage Load Regulation POUT Leakage Input Current Limit, High Level 1.3 2.7 1.5 3.0 1.0 0.15 0.2 0.780 200 0.28 0.3 0.800 10 333 0.05 3 3 1.7 3.3 1 1.6 2 0.45 0.4 0.812 50 500 150 V V A V A V nA A/V mV/V mV/A mV/A A ILIM_LO fOSC DCON(MIN) DCON(MAX) Input Current Limit, Low Level Oscillator Frequency Minimum Switch On Duty Cycle Maximum Switch On Duty Cycle 325 300 80 180 375 375 140 200 6 80 400 400 180 240 8 90 mA mA mA kHz % % 70 4267f 3 LTC4267 ELECTRICAL CHARACTERISTICS SYMBOL tRISE tFALL VIMAX ISLMAX tSFST TSHUTDOWN PARAMETER NGATE Drive Rise Time NGATE Drive Fall Time Peak Current Sense Voltage Peak Slope Compensation Output Current Soft-Start Time Thermal Shutdown Trip Temperature The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) CONDITIONS CLOAD = 3000pF, PVCC - PGND = 8V CLOAD = 3000pF, PVCC - PGND = 8V RSL = 0, PVCC - PGND = 8V (Note 16) PVCC - PGND = 8V (Note 17) PVCC - PGND = 8V (Notes 14, 18) MIN TYP 40 40 100 5 1.4 140 MAX UNITS ns ns mV A ms C 90 115 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: PVCC internal clamp circuit self regulates to 9.4V with respect to PGND. Note 3: The LTC4267 operates with a negative supply voltage in the range of - 1.5V to - 57V. To avoid confusion, voltages for the PD interface are always referred to in terms of absolute magnitude. Terms such as "maximum negative voltage" refer to the largest negative voltage and a "rising negative voltage" refers to a voltage that is becoming more negative. Note 4: The LTC4267 is designed to work with two polarity protection diode drops between the PSE and PD. Parameter ranges specified in the Electrical Characteristics section are with respect to this product pins and are designed to meet IEEE 802.3af specifications when these diode drops are included. See the Application Information section. Note 5: Signature resistance is measured via the two-point V/I method as defined by IEEE 802.3af. The PD signature resistance is offset from the 25k to account for diode resistance. With two series diodes, the total PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af specifications. The minimum probe voltages measured at the LTC4267 pins are -1.5V and -2.5V. The maximum probe voltages are -8.5V and -9.5V. Note 6: The PD interface includes hysteresis in the UVLO voltages to preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD will power up from a voltage source with 20 series resistance on the first trial. Note 7: Dynamic Supply current is higher due to the gate charge being delivered at the switching frequency. Note 8: IVPORTN_CLASS does not include classification current programmed at the RCLASS pin. Total current in classification mode will be IVPORTN_CLASS + ICLASS (See note 9). Note 9: ICLASS is the measured current flowing through RCLASS. ICLASS accuracy is with respect to the ideal current defined as ICLASS = 1.237/ RCLASS. The current accuracy does not include variations in RCLASS resistance. The total classification current for a PD also includes the IC quiescent current (IVPORTN_CLASS). See Applications Information. Note 10: For the DHC package, this parameter is assured by design and wafer level testing. Note 11: To disable the 25k signature, tie SIGDISA to VPORTP or hold SIGDISA high with respect to VPORTN. See Applications Information. Note 12: The switching regulator is tested in a feedback loop that servos VFB to the output of the error amplifier while maintaining ITH/RUN at the midpoint of the current limit range. Note 13: IPOUT_LEAK includes current drawn through POUT by the power good status circuit. This current is compensated for in the 25k signature resistance and does not affect PD operation. Note 14: The LTC4267 PD Interface includes thermal protection. In the event of an overtemperature condition, the PD interface will turn off the switching regulator until the part cools below the overtemperature limit. The LTC4267 is also protected against thermal damage from incorrect classification probing by the PSE. If the LTC4267 exceeds the overtemperature threshold, the classification load current is disabled. Note 15: The PD interface includes dual level input current limit. At turnon, before the POUT load capacitor is charged, the PD current level is set to a low level. After the load capacitor is charged and the POUT - VPORTN voltage difference is below the power good threshold, the PD switches to high level current limit. The PD stays in high level current limit until the input voltage drops below the UVLO turn-off threshold. Note 16: Peak current sense voltage is reduced dependent on duty cycle and an optional external resistor in series with the SENSE pin (RSL). For details, refer to the programmable slope compensation feature in the Applications Information section. Note 17: Guaranteed by design. Note 18: The PD interface includes overtemperature protection that is intended to protect the device from momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 4267f 4 LTC4267 TYPICAL PERFOR A CE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range 0.5 TA = 25C 50 0.4 INPUT CURRENT (mA) INPUT CURRENT (mA) INPUT CURRENT (mA) 0.3 0.2 0.1 0 0 -2 -6 -8 VPORTN VOLTAGE (V) -4 Input Current vs Input Voltage 3 EXCLUDES ANY LOAD CURRENT TA = 25C SIGNATURE RESISTANCE (k) 28 NORMALIZED UVLO THRESHOLD (%) INPUT CURRENT (mA) 2 1 0 -40 -50 -45 -55 VPORTN VOLTAGE (V) Power Good Output Low Voltage vs Current 4 TA = 25C 120 3 VOUT CURRENT (A) VPG_OUT (V) CURRENT LIMIT (mA) 2 1 0 0 2 6 4 CURRENT (mA) UW 8 Input Current vs Input Voltage TA = 25C CLASS 4 40 CLASS 3 12.0 11.5 11.0 10.5 10.0 9.5 CLASS 0 -10 4267 G01 Input Current vs Input Voltage CLASS 1 OPERATION 30 85C -40C 20 CLASS 2 CLASS 1 10 0 0 -10 -20 -30 -40 VPORTN VOLTAGE (V) -50 -60 9.0 -12 -14 -20 -18 -16 VPORTN VOLTAGE (V) -22 4267 G03 4267 G02 Signature Resistance vs Input Voltage RESISTANCE = V = V2 - V1 I I2 - I1 27 DIODES: S1B TA = 25C IEEE UPPER LIMIT 2 Normalized UVLO Threshold vs Temperature APPLICABLE TO TURN-ON AND TURN-0FF THRESHOLDS 1 26 25 24 LTC4267 ONLY 23 22 V1: -1 V2: -2 IEEE LOWER LIMIT LTC4267 + 2 DIODES 0 -1 -60 4267 G04 -3 -4 -7 -5 -8 -6 VPORTN VOLTAGE (V) -9 -10 4267 G05 -2 -40 -20 60 0 20 40 TEMPERATURE (C) 80 4267 G06 POUT Leakage Current VIN = 0V TA = 25C 400 Current Limit vs Input Voltage 85C - 40C HIGH CURRENT MODE 90 300 60 200 85C - 40C 30 LOW CURRENT MODE 10 4267 G07 0 0 40 POUT PIN VOLTAGE (V) 20 60 4267 G08 100 -40 -50 -45 -55 VPORTN VOLTAGE (V) -60 4267 G09 4267f 5 LTC4267 TYPICAL PERFOR A CE CHARACTERISTICS Reference Voltage vs Temperature 812 808 VFB VOLTAGE (mV) VFB VOLTAGE (mV) 804 800 796 792 788 -50 -30 -10 PVCC = 8V 801.0 800.8 800.6 800.4 800.2 800.0 799.8 799.6 799.4 799.2 10 30 50 70 90 110 799.0 6 6.5 8 7.5 8.5 9 PVCC SUPPLY VOLTAGE (V) 7 9.5 4267 G11 OSCILLATOR FREQUENCY (kHz) TEMPERATURE (C) 4267 G10 Oscillator Frequency vs Supply Voltage 210 208 OSCILLATOR FREQUENCY (kHz) 206 204 202 200 198 196 194 192 190 6 6.5 7.5 8 8.5 7 PVCC SUPPLY VOLTAGE (V) 9 4267 G14 TA = 25C PVCC UNDERVOLTAGE LOCKOUT (V) 7.5 7.0 6.5 6.0 5.5 5.0 -50 -30 -10 10 30 50 80 TEMPERATURE (C) 90 110 VTURNOFF PVCC (V) SUPPLY CURRENT (A) 6 UW Reference Voltage vs Supply Voltage 240 TA = 25C PVCC VCLAMP1mA 230 220 210 200 190 Oscillator Frequency vs Temperature PVCC = 8V (WITH RESPECT TO PGND) 180 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 4267 G13 PVCC Undervoltage Lockout Thresholds vs Temperature 10.0 9.5 9.0 8.5 8.0 VTURNON 10.0 9.9 9.8 9.7 9.6 9.5 9.4 9.3 9.2 9.1 PVCC Shunt Regulator Voltage vs Temperature IPVCC = 1mA 9.0 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 4267 G16 4267 G17 IPVCC Supply Current vs Temperature 265 260 255 250 245 240 235 230 225 220 215 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 PVCC = 8V VITH/RUN = 1.3V 4267 G18 4267f LTC4267 TYPICAL PERFOR A CE CHARACTERISTICS Start-Up IPVCC Supply Current vs Temperature 60 START-UP SUPPLY CURRENT (A) 50 40 30 20 10 0 -50 -30 -10 10 30 50 70 TEMPERATURE (C) PVCC = VTURNON - 0.1V SHUTDOWN THRESHOLD (mV) 450 400 350 300 250 200 150 100 -50 -30 -10 ITH/RUN PIN CURRENT SOURCE (nA) Peak Current Sense Voltage vs Temperature 120 115 SENSE PIN VOLTAGE (mV) SOFT-START TIME (ms) 110 105 100 95 90 85 80 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 PVCC = 8V 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 UW 90 ITH/RUN Shutdown Threshold vs Temperature 600 500 400 300 200 100 ITH/RUN Start-Up Current Source vs Temperature PVCC = VTURNON + 0.1V VITH/RUN = 0V 110 10 30 50 70 90 110 TEMPERATURE (C) 4267 G19 4267 G20 0 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 4267 G21 Soft-Start Time vs Temperature 0 -50 -30 -10 10 30 50 70 TEMPERATURE (C) 90 110 4267 G22 4267 G23 4267f 7 LTC4267 PI FU CTIO S ITH/RUN (Pin 2/Pin 1): Current Threshold/Run Input. This pin performs two functions. It serves as the switching regulator error amplifier compensation point as well as the run/shutdown control input. Nominal voltage range is 0.7V to 1.9V. Forcing the pin below 0.28V with respect to PGND causes the controller to shut down. PGND (Pin 1, 8, 9, 16/Pin 2, 15): Switching Regulator Negative Supply. This pin is the negative supply rail for the switching regulator controller and must be tied to POUT. NGATE (Pin 3/Pin 3): Gate Driver Output. This pin drives the regulator's external N-Channel MOSFET and swings from PGND to PVCC. PVCC (Pin 4/Pin 4): Switching Regulator Positive Supply. This pin is the positive supply rail for the switching regulator and must be closely decoupled to PGND. RCLASS (Pin 5/Pin 5): Class Select Input. Used to set the current value the PD maintains during classification. Connect a resistor between RCLASS and VPORTN (see Table 2). VPORTN (Pin 7/Pin 7): Negative Power Input. Tie to the -48V input port through the input diodes. POUT (Pin 10/Pin 10): Power Output. Supplies -48V to the switching regulator PGND pin and any additional PD loads through an internal power MOSFET that limits input current. POUT is high impedance until the voltage reaches the turn-on UVLO threshold. The output is then current limited. See the Application Information section. 8 U U U (GN/DHC) PWRGD (Pin 11/Pin 11): Power Good Output, Open-Drain. Indicates that the PD MOSFET is on and the switching regulator can start operation. Low impedance indicates power is good. PWRGD is high impedance during detection, classification and in the event of a thermal overload. PWRGD is referenced to VPORTN. SIGDISA (Pin 12/Pin 12): Signature Disable Input. SIGDISA allows the PD to present an invalid signature resistance and remain inactive. Connecting SIGDISA to VPORTP lowers the signature resistance to an invalid value and disables all functions of the LTC4267. If unused, tie SIGDISA to VPORTN. VPORTP (Pin 13/Pin 13): Positive Power Input. Tie to the input port power return through the input diodes. SENSE (Pin 14/Pin 14): Current Sense. This pin performs two functions. It monitors the regulator switch current by reading the voltage across an external sense resistor. It also injects a current ramp that develops a slope compensation voltage across an optional external programming resistor. See the Applications Information section. VFB (Pin 15/Pin 16): Feedback Input. Receives the feedback voltage from the external resistor divider across the output. NC (Pin 6/Pin 6, 8, 9): No Internal Connection. Backside Connection (DHC Only, Pin 17): Exposed Pad. This exposed pad must be soldered to an electrically isolated and thermally conductive PC board heat sink. 4267f LTC4267 BLOCK DIAGRA CLASSIFICATION CURRENT LOAD 1.237V + - EN 25k SIGNATURE RESISTOR 9k 16k 800mV REFERENCE VCC SHUNT REGULATOR RCLASS CONTROL CIRCUITS + 375mA INPUT CURRENT LIMIT VFB - ITH/RUN + 140mA EN - VPORTN POUT BOLD LINE INDICATES HIGH CURRENT PATH PGND 20mV 1.2V APPLICATIO S I FOR ATIO OVERVIEW The LTC4267 is partitioned into two major blocks: a Powered Device (PD) interface controller and a current mode flyback switching regulator. The Powered Device (PD) interface is intended for use as the front end of a PD adhering to the IEEE 802.3af standard, and includes a trimmed 25k signature resistor, classification current source, and an input current limit circuit. With these functions integrated into the LTC4267, the signature and power interface for a PD can be built that meets all the requirements of the IEEE 802.3af specification with a minimum of external components. The switching regulator portion of the LTC4267 is a constant frequency current mode controller that is optimized for Power over Ethernet applications. The regulator is designed to drive a 6V N-channel MOSFET and features soft-start and programmable slope compensation. The integrated error amplifier and precision reference give the PD designer the option of using a nonisolated topology without the need for an external amplifier or reference. The LTC4267 has been specifically designed to interface with both IEEE compliant Power Sourcing Equipment (PSE) and legacy PSEs which do not meet the inrush current requirement of the IEEE 802.3af specification. By setting the initial inrush current limit to a low level, a PD using the LTC4267 minimizes the current drawn from the PSE during start-up. After powering up, the LTC4267 switches to the high level current limit, thereby allowing the PD to consume up to 12.95W if an IEEE 802.3af PSE is present. This low level current limit also allows the LTC4267 to charge arbitrarily large load capacitors without exceeding the inrush limits of the IEEE 802.3af specification. This dual level current limit provides the system designer with flexibility to design PDs which are compatible with legacy PSEs while also being able to take advantage of the higher power available in an IEEE 802.3af system. Using an LTC4267 for the power and signature interface functions of a PD provides several advantages. The LTC4267 current limit circuit includes an onboard 100V, 400mA power MOSFET. This low leakage MOSFET is 4267f + - U W W VPORTP SIGDISA PVCC 0.3A 0.28V + - SHUTDOWN COMPARATOR PVCC < VTURNON UNDERVOLTAGE LOCKOUT PWRGD POWER GOOD SOFTSTART CLAMP SHUTDOWN ERROR AMPLIFIER CURRENT COMPARATOR R Q S SWITCHING LOGIC AND BLANKING CIRCUIT PVCC NGATE GATE DRIVER 200kHz OSCILLATOR SLOPE COMP CURRENT RAMP SENSE 4267 BD UU 9 LTC4267 APPLICATIO S I FOR ATIO specified to avoid corrupting the 25k signature resistor while also saving board space and cost. In addition, the inrush current limit requirement of the IEEE 802.3af standard can cause large transient power dissipation in the PD. The LTC4267 is designed to allow multiple turn-on sequences without overheating the miniature 16-lead package. In the event of excessive power cycling, the LTC4267 provides thermal overload protection to keep the onboard power MOSFET within its safe operating area. OPERATION The LTC4267 PD interface has several modes of operation depending on the applied input voltage as shown in Figure 1 and summarized in Table 1. These modes satisfy the requirements defined in the IEEE 802.3af specification. The input voltage is applied to the VPORTN pin and must be negative relative to the VPORTP pin. Voltages in the data sheet for the PD interface portion of the LTC4267 are with respect to VPORTP while the voltages for the switching regulator are referenced to PGND. It is assumed that PGND is tied to POUT. Note the use of different ground symbols throughout the data sheet. PD CURRENT VPORTN (V) POUT (V) PWRGD (V) Table 1. LTC4267 Operational Mode as a Function of Input Voltage INPUT VOLTAGE (VPORTN with RESPECT to VPORTP) LTC4267 MODE OF OPERATION 0V to - 1.4V Inactive -1.5V to -10V 25k Signature Resistor Detection -11V to -12.4V Classification Load Current Ramps up from 0% to 100% -12.5V to UVLO* Classification Load Current Active UVLO* to -57V Power Applied to Switching Regulator * VPORTN UVLO includes hysteresis. Rising input threshold - 36.0V Falling input threshold -30.5V 10 U DETECTION V1 -10 -20 -30 -40 -50 TIME -10 -20 -30 -40 -50 TIME -10 -20 -30 -40 -50 PWRGD TRACKS VPORTN CURRENT LIMIT, ILIM_LO LOAD, ILOAD (UP TO ILIM_HI) ICLASS CLASSIFICATION ICLASS DETECTION I2 DETECTION I1 VOLTAGES WITH RESPECT TO VPORTP I1 = I2 = V1 - 2 DIODE DROPS 25k TIME POWER BAD POWER GOOD POWER BAD UVLO OFF dV = ILIMIT C1 dt UVLO ON = RLOAD C1 UVLO OFF UVLO TURN-ON DETECTION V2 CLASSIFICATION UVLO TURN-OFF TIME ILIM_LO V2 - 2 DIODE DROPS 25k ICLASS DEPENDENT ON RCLASS SELECTION ILIM_LO = 140mA (NOMINAL), ILIM_HI = 375mA (NOMINAL) ILOAD = VIN (UP TO ILIM_HI) RLOAD IIN PSE VIN R CLASS RCLASS VPORTP LTC4267 PWRGD VPORTN POUT PGND 4267 F01 W UU R9 C1 VOUT Figure 1. Output Voltage, PWRGD and PD Current as a Function of Input Voltage 4267f LTC4267 APPLICATIO S I FOR ATIO Series Diodes The IEEE 802.3af-defined operating modes for a PD reference the input voltage at the RJ45 connector on the PD. The PD must be able to accept power of either polarity at each of its inputs, so it is common to install diode bridges (Figure 2). The LTC4267 takes this into account by compensating for these diode drops in the threshold points for each range of operation. A similar adjustment is made for the UVLO voltages. Detection During detection, the PSE will apply a voltage in the range of -2.8V to -10V on the cable and look for a 25k signature resistor. This identifies the device at the end of the cable as a PD. With the terminal voltage in this range, the LTC4267 connects an internal 25k resistor between the VPORTP and VPORTN pins. This precision, temperature compensated resistor presents the proper signature to alert the PSE that a PD is present and desires power to be applied. The internal low-leakage UVLO switch prevents the switching regulator circuitry from affecting the detection signature. The LTC4267 is designed to compensate for the voltage and resistance effects of the IEEE required diode bridge. RJ45 1 TX+ TX- RX+ RX- VPORTP 4 5 SPARE+ BR2 D3 4 7 8 SPARE- VPORTN 4267 F02 2 3 POWERED DEVICE (PD) INTERFACE AS DEFINED BY IEEE 802.3af 6 Figure 2. LTC4267 PD Front End Using Diode Bridges on Main and Spare Inputs U The signature range extends below the IEEE range to accommodate the voltage drop of the two diodes. The IEEE specification requires the PSE to use a V/I measurement technique to keep the DC offset of these diodes from affecting the signature resistance measurement. However, the diode resistance appears in series with the signature resistor and must be included in the overall signature resistance of the PD. The LTC4267 compensates for the two series diodes in the signature path by offsetting the resistance so that a PD built using the LTC4267 will meet the IEEE specification. In some applications it is necessary to control whether or not the PD is detected. In this case, the 25k signature resistor can be enabled and disabled with the use of the SIGDISA pin (Figure 3). Disabling the signature via the SIGDISA pin will change the signature resistor to 9k (typical) which is an invalid signature per the IEEE 802.3af specification. This invalid signature is present for PD input voltages from -2.8V to -10V. If the input rises above -10V, the signature resistor reverts to 25k to minimize power dissipation in the LTC4267. To disable the signature, tie SIGDISA to VPORTP. Alternately, the SIGDISA pin can be driven high with respect to VPORTN. When SIGDISA is high, all functions of the PD interface are disabled. T1 BR1 TO PHY 8 LTC4267 4267f W UU 11 LTC4267 APPLICATIO S I FOR ATIO LTC4267 9k 25k SIGNATURE RESISTOR 16k VPORTN 4267 F03 VPORTP SIGNATURE DISABLE SIGDISA TO PSE Figure 3. 25k Signature Resistor with Disable Classification Once the PSE has detected a PD, the PSE may optionally classify the PD. Classification provides a method for more efficient allocation of power by allowing the PSE to identify lower power PDs and allocate less power for these devices. The IEEE 802.3af specification defines five classes (Table 2) with varying power levels. The designer selects the appropriate classification based on the power consumption of the PD. For each class, there is an associated load current that the PD asserts onto the line during classification probing. The PSE measures the PD load current to determine the proper classification and PD power requirements. During classification (Figure 4), the PSE presents a fixed voltage between -15.5V and -20.5V to the PD. With the input voltage in this range, the LTC4267 asserts a load current from the VPORTP pin through the RCLASS resistor. The magnitude of the load current is set by the RCLASS resistor. The resistor values associated with each class are shown in Table 2. Note that the switching regulator will not interfere with the classification measurement since the LTC4267 has not passed power to the regulator. Table 2. Summary of IEEE 802.3af Power Classifications and LTC4267 RCLASS Resistor Selection Maximum Nominal Power Levels Classification at Input of PD Load Current Class Usage (W) (mA) 0 Default 0.44 to 12.95 <5 1 Optional 0.44 to 3.84 10.5 2 Optional 3.84 to 6.49 18.5 3 Optional 6.49 to 12.95 28 4 Reserved Reserved* 40 *Class 4 is currently reserved and should not be used. LTC4267 RCLASS Resistor (, 1%) Open 124 68.1 45.3 30.9 12 U CURRENT PATH PSE PROBING VOLTAGE SOURCE -15.5V TO -20.5V RCLASS VPORTN LTC4267 RCLASS VPORTP CONSTANT LOAD CURRENT INTERNAL TO LTC4267 W UU V PSE CURRENT MONITOR PSE PD 4267 F04 Figure 4. IEEE 802.3af Classification Probing The IEEE 802.3af specification limits the classification time to 75ms because a significant amount of power is dissipated in the PD. The LTC4267 is designed to handle the power dissipation for this time period. If the PSE probing exceeds 75ms, the LTC4267 may overheat. In this situation, the thermal protection circuit will engage and disable the classification current source in order to protect the part. The LTC4267 stays in classification mode until the input voltage rises above the UVLO turn-on voltage. VPORTN Undervoltage Lockout The IEEE specification dictates a maximum turn-on voltage of 42V and a minimum turn-off voltage of 30V for the PD. In addition, the PD must maintain large on-off hysteresis to prevent resistive losses in the wiring between the PSE and the PD from causing start-up oscillation. The LTC4267 incorporates an undervoltage lockout (UVLO) circuit that monitors the line voltage at VPORTN to determine when to apply power to the integrated switching regulator (Figure 5). Before the power is applied to the switching regulator, the POUT pin is high impedance and sitting at the ground potential since there is no charge on capacitor C1. When the input voltage rises above the UVLO turn-on threshold, the LTC4267 removes the detection and classification loads and turns on the internal power MOSFET. C1 charges up under the LTC4267 current limit control and the POUT pin transitions from 0V to VPORTN. This sequence is shown in Figure 1. The LTC4267 includes a hysteretic UVLO circuit on VPORTN that keeps power applied to the load until the input voltage falls below the UVLO turn-off threshold. Once the input voltage drops below -30V, the internal power MOSFET is turned off and 4267f LTC4267 APPLICATIO S I FOR ATIO the classification current is reenabled. C1 will discharge through the PD circuitry and the POUT pin will go to a high impedance state. LTC4267 TO PSE VPORTP C1 5F MIN + UNDERVOLTAGE LOCKOUT CIRCUIT VPORTN PGND POUT 4267 F05 INPUT LTC4267 VOLTAGE POWER MOSFET 0V TO UVLO* OFF >UVLO* ON *UVLO INCLUDES HYSTERESIS RISING INPUT THRESHOLD -36V FALLING INPUT THRESHOLD -30.5V CURRENT-LIMITED TURN ON Figure 5. LTC4267 VPORTN Undervoltage Lockout Input Current Limit IEEE 802.3af specifies a maximum inrush current and also specifies a minimum load capacitor between the VPORTP and POUT pins. To control turn-on surge current in the system, the LTC4267 integrates a dual level current limit circuit with an onboard power MOSFET and sense resistor to provide a complete inrush control circuit without additional external components. At turn-on, the LTC4267 will limit the input current to the low level, allowing the load capacitor to ramp up to the line voltage in a controlled manner. The LTC4267 has been specifically designed to interface with legacy PSEs which do not meet the inrush current requirement of the IEEE 802.3af specification. At turn-on the LTC4267 current limit is set to the lower level. After C1 is charged up and the POUT - VPORTN voltage difference is below the power good threshold, the LTC4267 switches to the high level current limit. The dual level current limit allows legacy PSEs with limited current sourcing capability to power up the PD while also allowing the PD to draw full power from an IEEE 802.3af PSE. The dual level current limit also allows use of arbitrarily large load capacitors. The IEEE 802.3af specification mandates that at turn-on the PD not exceed the inrush current limit for more than 50ms. The LTC4267 is not restricted to the 50ms time U limit because the load capacitor is charged with a current below the IEEE inrush current limit specification. As the LTC4267 switches from the low to high level current limit, the current will increase momentarily. This current spike is a result of the LTC4267 charging the last 1.5V at the high level current limit. When charging a 10F capacitor, the current spike is typically 100s wide and 125% of the nominal low level current limit. The LTC4267 stays in the high level current limit mode until the input voltage drops below the UVLO turn-off threshold. This dual level current limit provides the system designer with the flexibility to design PDs which are compatible with legacy PSEs while also being able to take advantage of the higher power allocation available in an IEEE 802.3af system. During the current limited turn on, a large amount of power is dissipated in the power MOSFET. The LTC4267 PD interface is designed to accept this thermal load and is thermally protected to avoid damage to the onboard power MOSFET. Note that in order to adhere to the IEEE 802.3af standard, it is necessary for the PD designer to ensure the PD steady state power consumption falls within the limits shown in Table 2. In addition, the steady state current must be less than ILIM_HI. Power Good The LTC4267 PD Interface includes a power good circuit (Figure 6) that is used to indicate that load capacitor C1 is fully charged and that the switching regulator can start operation. The power good circuit monitors the voltage across the internal UVLO power MOSFET and PWRGD is asserted when the voltage falls below 1.5V. The power good circuit includes hysteresis to allow the LTC4267 to operate near the current limit point without inadvertently disabling PWRGD. The MOSFET voltage must increase to 3V before PWRGD is disabled. If a sudden increase in voltage appears on the input line, this voltage step will be transferred through capacitor C1 and appear across the power MOSFET. The response of the LTC4267 will depend on the magnitude of the voltage step, the rise time of the step, the value of capacitor C1 and the switching regulator load. For fast rising inputs, 4267f W UU 13 LTC4267 APPLICATIO S I FOR ATIO LTC4267 PWRGD THERMAL SHUTDOWN UVLO TO PSE ITH/RUN R9 100k TO PSE C1 5F MIN ITH/RUN VPORTP R9 100k Q1 2N7002 C17 C15 0.047F D6 MMBD4148 ITH/RUN LTC3803 GND OPTIONAL AUXILIARY SWITCHING REGULATOR - + PGND + - 1.125V 300k 300k POUT 4267 F06 VPORTN Figure 6. LTC4267 Power Good TO PSE the LTC4267 will attempt to quickly charge capacitor C1 using an internal secondary current limit circuit. In this scenario, the PSE current limit should provide the overall limit for the circuit. For slower rising inputs, the 375mA current limit in the LTC4267 will set the charge rate of the capacitor C1. In either case, the PWRGD signal may go inactive briefly while the capacitor is charged up to the new line voltage. In the design of a PD, it is necessary to determine if a step in the input voltage will cause the PWRGD signal to go inactive and how to respond to this event. In some designs, it may be desirable to filter the PWRGD signal so that intermittent power bad conditions are ignored. Figure 7 demonstrates a method to insert a lowpass filter on the power good interface. For PD designs that use a large load capacitor and also consume a lot of power, it is important to delay activation of the switching regulator with the PWRGD signal. If the regulator is not disabled during the current-limited turn-on sequence, the PD circuitry will rob current intended for charging up the load capacitor and create a slow rising input, possibly causing the LTC4267 to go into thermal shutdown. The PWRGD pin connects to an internal open drain, 100V transistor capable of sinking 1mA. Low impedance to VPORTN indicates power is good. PWRGD is high impedance during signature and classification probing and in the event of a thermal overload. During turn-off, PWRGD is deactivated when the input voltage drops below 30V. In addition, PWRGD may go active briefly at turn-on for fast rising input waveforms. PWRGD is referenced to the VPORTN pin and when active, will be near the VPORTN potential. Connect the PWRGD pin to the switching regulator circuitry as shown in Figure 7. 14 U + -48V PWRGD LTC4267 PGND VPORTN POUT PGND ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP PGND RSTART PVCC VPORTP R9 100k Q1 2N7002 CPVCC C1 R18 5F 10k 100V C15 0.047F D6 MMBD4148 W UU + C1 R18 5F 10k 100V PWRGD LTC4267 PGND -48V VPORTN POUT + PGND ALTERNATE ACTIVE-HIGH ENABLE FOR PVCC PIN SEE APPLICATIONS INFORMATION SECTION 4267 F07 Figure 7. Power Good Interface Examples PD Interface Thermal Protection The LTC4267 PD Interface includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. Several factors create the possibility of significant power dissipation within the LTC4267. At turn-on, before the load capacitor has charged up, the instantaneous power dissipated by the LTC4267 can be as much as 10W. As the load capacitor charges up, the power dissipation in the LTC4267 will decrease until it reaches a steady-state value dependent on the DC load current. The size of the load capacitor determines how fast the power dissipation in the LTC4267 will subside. At room temperature, the LTC4267 can typically handle load capacitors as large as 800F without going into thermal shutdown. With large load capacitors, the LTC4267 die temperature will increase by as much as 50C during a single turn-on sequence. If for some reason power were removed from the part and then quickly reapplied so that the LTC4267 had to charge up the load capacitor again, the temperature rise would be excessive if safety precautions were not implemented. The LTC4267 PD interface protects itself from thermal damage by monitoring the die temperature. If the die 4267f LTC4267 APPLICATIO S I FOR ATIO temperature exceeds the overtemperature trip point, the current is reduced to zero and very little power is dissipated in the part until it cools below the overtemperature set point. Once the LTC4267 has charged up the load capacitor and the PD is powered and running, there will be minor residual heating due to the DC load current of the PD flowing through the internal MOSFET. The DHC package offers superior thermal performance by including an exposed pad that is soldered to an electrically isolated heat sink on the printed circuit board. During classification, excessive heating of the LTC4267 can occur if the PSE violates the 75ms probing time limit. To protect the LTC4267, thermal overload circuitry will disable classification current if the die temperature exceeds the overtemperature trip point. When the die cools down below the trip point, classification current is reenabled. The PD is designed to operate at a high ambient temperature and with the maximum allowable supply (57V). However, there is a limit to the size of the load capacitor that can be charged up before the LTC4267 reaches the overtemperature trip point. Hitting the overtemperature trip point intermittently does not harm the LTC4267, but it will delay the completion of capacitor charging. Capacitors up to 200F can be charged without a problem over the full operating temperature range. Switching Regulator Main Control Loop Due to space limitations, the basics of current mode DC/DC conversion will not be discussed here. The reader is referred to the detail treatment in Application Note 19 or in texts such as Abraham Pressman's Switching Power Supply Design. In a Power over Ethernet System, the majority of applications involve an isolated power supply design. This means that the output power supply does not have any DC electrical path to the PD interface or the switching regulator primary. The DC isolation is achieved typically through a transformer in the forward path and an optoisolator in the feedback path or a third winding in the transformer. The typical application circuit shown on the front page of the datasheet represents an isolated design using an optoisolator. In applications where a nonisolated U topology is desired, the LTC4267 features a feedback port and an internal error amplifier that can be enabled for this specific application. In the typical application circuit (Figure 11), the isolated topology employs an external resistive voltage divider to present a fraction of the output voltage to an external error amplifier. The error amplifier responds by pulling an analog current through the input LED on an optoisolator. The collector of the optoisolator output presents a corresponding current into the ITH/RUN pin via a series diode. This method generates a feedback voltage on the ITH/RUN pin while maintaining isolation. The voltage on the ITH/RUN pin controls the pulse-width modulator formed by the oscillator, current comparator, and RS latch. Specifically, the voltage at the ITH/RUN pin sets the current comparator's trip threshold. The current comparator monitors the voltage across a sense resistor in series with the source terminal of the external N-Channel MOSFET. The LTC4267 turns on the external power MOSFET when the internal free-running 200kHz oscillator sets the RS latch. It turns off the MOSFET when the current comparator resets the latch or when 80% duty cycle is reached, whichever happens first. In this way, the peak current levels through the flyback transformer's primary and secondary are controlled by the ITH/RUN voltage. In applications where a nonisolated topology is desirable (Figure 11), an external resistive voltage divider can present a fraction of the output voltage directly to the VFB pin of the LTC4267. The divider must be designed so when the output is at its desired voltage, the VFB pin voltage will equal the 800mV onboard internal reference. The internal error amplifier responds by driving the ITH/RUN pin. The LTC4267 switching regulator performs in a similar manner as described previously. Regulator Start-Up/Shutdown The LTC4267 switching regulator has two shutdown mechanisms to enable and disable operation: an undervoltage lockout on the PVCC supply pin and a forced shutdown whenever external circuitry drives the ITH/RUN pin low. The LTC4267 switcher transitions into and out of shutdown according to the state diagram (Figure 8). It is 4267f W UU 15 LTC4267 APPLICATIO S I FOR ATIO important not to confuse the undervoltage lockout of the PD interface at VPORTN with that of the switching regulator at PVCC. They are independent functions. LTC4267 PWM SHUTDOWN PVCC < VTURNOFF VITH/RUN < VITHSHDN (NOMINALLY 0.28V) VITH/RUN > VITHSHDN AND PVCC > VTURNON (NOMINALLY 8.7V) ALL VOLTAGES WITH RESPECT TO PGND LTC4267 PWM ENABLED 4267 F08 Figure 8. LTC4267 Switching Regulator Start-Up/Shutdown State Diagram The undervoltage lockout mechanism on PVCC prevents the LTC4267 switching regulator from trying to drive the external N-Channel MOSFET with insufficient gate-tosource voltage. The voltage at the PVCC pin must exceed VTURNON (nominally 8.7V with respect to PGND) at least momentarily to enable operation. The PVCC voltage must fall to VTURNOFF (nominally 5.7V with respect to PGND) before the undervoltage lockout disables the switching regulator. This wide UVLO hysteresis range supports applications where a bias winding on the flyback transformer is used to increase the efficiency of the LTC4267 switching regulator. The ITH/RUN can be driven below VITHSHDN (nominally 0.28V with respect to PGND) to force the LTC4267 switching regulator into shutdown. An internal 0.3A current source always tries to pull the ITH/RUN pin towards PVCC. When the ITH/RUN pin voltage is allowed to exceed VITHSHDN and PVCC exceeds VTURNON, the LTC4267 switching regulator begins to operate and an internal clamp immediately pulls the ITH/RUN pin to about 0.7V. In operation, the ITH/RUN pin voltage will vary from roughly 0.7V to 1.9V to represent current comparator thresholds from zero to maximum. Internal Soft-Start An internal soft-start feature is enabled whenever the LTC4267 switching regulator comes out of shutdown. Specifically, the ITH/RUN voltage is clamped and is 16 U prevented from reaching maximum until 1.4ms have passed. This allows the input current of the PD to rise in a smooth and controlled manner on start-up and stay within the current limit requirement of the LTC4267 interface. Adjustable Slope Compensation The LTC4267 switching regulator injects a 5A peak current ramp out through its SENSE pin which can be used for slope compensation in designs that require it. This current ramp is approximately linear and begins at zero current at 6% duty cycle, reaching peak current at 80% duty cycle. Programming the slope compensation via a series resistor is discussed in the External Interface and Component Selection section. EXTERNAL INTERFACE AND COMPONENT SELECTION Input Interface Transformer Nodes on an Ethernet network commonly interface to the outside world via an isolation transformer (Figure 9). For PoE devices, the isolation transformer must include a center tap on the media (cable) side. Proper termination is required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. Transformer vendors such as Pulse, Bel Fuse, Tyco and others (Table 3) can provide assistance with selection of an appropriate isolation transformer and proper termination methods. These vendors have transformers specifically designed for use in PD applications. Table 3. Power over Ethernet Transformer Vendors VENDOR Pulse Engineering CONTACT INFORMATION 12220 World Trade Drive San Diego, CA 92128 Tel: 858-674-8100 FAX: 858-674-8262 http://www.pulseeng.com 206 Van Vorst Street Jersey City, NJ 07302 Tel: 201-432-0463 FAX: 201-432-9542 http://www.belfuse.com 308 Constitution Drive Menlo Park, CA 94025-1164 Tel: 800-227-7040 FAX: 650-361-2508 http://www.circuitprotection.com 4267f W UU Bel Fuse Inc. Tyco Electronics LTC4267 APPLICATIO S I FOR ATIO Diode Bridge IEEE 802.3af allows power wiring in either of two configurations: on the TX/RX wires or via the spare wire pairs in the RJ45 connector. The PD is required to accept power in either polarity on either the main or spare inputs; therefore it is common to install diode bridges on both inputs in order to accommodate the different wiring configurations. Figure 9 demonstrates an implementation of these diode bridges. The IEEE 802.3af specification also mandates that the leakage back through the unused bridge be less than 28A when the PD is powered with 57V. The IEEE standard includes an AC impedance requirement in order to implement the AC disconnect function. Capacitor C14 in Figure 9 is used to meet this AC impedance requirement. A 0.1F capacitor is recommended for this application. The LTC4267 has several different modes of operation based on the voltage present between VPORTN and VPORTP pins. The forward voltage drop of the input diodes in a PD design subtracts from the input voltage and will affect the transition point between modes. When using the LTC4267, it is necessary to pay close attention to this forward voltage drop. Selection of oversized diodes will help keep the PD thresholds from exceeding IEEE specifications. The input diode bridge of a PD can consume over 4% of the available power in some applications. It may be desirable to use Schottky diodes in order to reduce power loss. However, if the standard diode bridge is replaced with a Schottky bridge, the transition points between the modes will be affected. Figure 10 shows a technique for using Schottky diodes while maintaining proper threshold points to meet IEEE 802.3af compliance. D13 is added to compensate for the change in UVLO turn-on voltage caused by the Schottky diodes and consumes little power. Classification Resistor Selection (RCLASS) The IEEE specification allows classifying PDs into four distinct classes with class 4 being reserved for future use (Table 2). An external resistor connected from RCLASS to VPORTN (Figure 4) sets the value of the load current. The designer should determine which power category the PD U falls into and then select the appropriate value of RCLASS from Table 2. If a unique load current is required, the value of RCLASS can be calculated as: RCLASS = 1.237V/(IDESIRED - IIN_CLASS) where IIN_CLASS is the LTC4267 IC supply current during classification and is given in the electrical specifications. The RCLASS resistor must be 1% or better to avoid degrading the overall accuracy of the classification circuit. Resistor power dissipation will be 50mW maximum and is transient so heating is typically not a concern. In order to maintain loop stability, the layout should minimize capacitance at the RCLASS node. The classification circuit can be disabled by floating the RCLASS pin. The RCLASS pin should not be shorted to VPORTN as this would force the LTC4267 classification circuit to attempt to source very large currents and quickly go into thermal shutdown. Power Good Interface The PWRGD signal is controlled by a high voltage, opendrain transistor. The designer has the option of using this signal to enable the onboard switching regulator through the ITH/RUN or the PVCC pins. Examples of active-high interface circuits for controlling the switching regulator are shown in Figure 7. In some applications, it is desirable to ignore intermittent power bad conditions. This can be accomplished by including capacitor C15 in Figure 7 to form a lowpass filter. With the components shown, power bad conditions less than about 200s will be ignored. Conversely, in other applications it may be desirable to delay assertion of PWRGD to the switching regulator using CPVCC or C17 as shown in Figure 7. It is recommended that the designer use the power good signal to enable the switching regulator. Using PWRGD ensures the capacitor C1 has reached within 1.5V of the final value and is ready to accept a load. The LTC4267 is designed with wide power good hysteresis to handle sudden fluctuations in the load voltage and current without prematurely shutting off the switching regulator. Please refer to the Power-Up Sequencing of the Application Information section. 4267f W UU 17 LTC4267 APPLICATIO S I FOR ATIO RJ45 1 TX+ TX- RX+ RX- 16 T1 1 15 2 3 14 11 10 6 9 2 3 6 7 8 VPORTP BR2 HD01 TO PHY BR1 HD01 PULSE H2019 SPARE+ 4 5 7 8 SPARE- Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor R2 75 C3 0.01F 200V R1 75 C7 0.01F 200V C2 1000pF 2kV J2 1 T1 OUT TO PHY TXOUT+ - TX+ TX- RX+ RX- 16 15 1 2 3 2 14 TXOUT IN FROM PSE 3 11 10 6 7 8 RXOUT+ RXOUT- 6 4 5 7 8 RJ45 9 SPARE+ SPARE- D15 B1100 NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTORS ARE 5% 2. SELECT RCLASS FOR CLASS 1-4 OPERATION. REFER TO DATA SHEET APPLICATIONS INFORMATION SECTION C2: AVX 1808GC102MAT D9 TO D12, D14 TO D17: DIODES INC., B1100 T1: PULSE H2019 Figure 10. PD Front End with Isolation Transformer, 2nd Schottky Diode Bridge 4267f 18 U C14 0.1F 100V LTC4267 D3 SMAJ58A TVS VPORTN 4267 F09 W UU D9 B1100 D11 B1100 D10 B1100 D12 B1100 D6 SMAJ58A C11 0.1F 100V D13 MMSD4148 C25 0.01F 200V R31 75 C24 0.01F 200V R30 75 D14 B1100 RCLASS D17 B1100 D16 B1100 RCLASS 1% VPORTP LTC4267 VPORTN 4267 F10 LTC4267 APPLICATIO S I FOR ATIO Signature Disable Interface To disable the 25k signature resistor, connect SIGDISA pin to the VPORTP pin. Alternately, SIGDISA pin can be driven high with respect to VPORTN. An example of a signature disable interface is shown in Figure 16, option 2. Note that the SIGDISA input resistance is relatively large and the threshold voltage is fairly low. Because of high voltages present on the printed circuit board, leakage currents from the VPORTP pin could inadvertently pull SIGDISA high. To ensure trouble-free operation, use high voltage layout techniques in the vicinity of SIGDISA. If unused, connect SIGDISA to VPORTN. Load Capacitor The IEEE 802.3af specification requires that the PD maintain a minimum load capacitance of 5F (provided by C1 in Figure 11). It is permissible to have a much larger load capacitor and the LTC4267 can charge very large load capacitors before thermal issues become a problem. The load capacitor must be large enough to provide sufficient energy for proper operation of the switching regulator. However, the capacitor must not be too large or the PD design may violate IEEE 802.3af requirements. If the load capacitor is too large, there can be a problem with inadvertent power shutdown by the PSE. Consider the following scenario. If the PSE is running at -57V (maximum allowed) and the PD has detected and powered up, the load capacitor will be charged to nearly -57V. If for some reason the PSE voltage is suddenly reduced to -44V (minimum allowed), the input bridge will reverse bias and the PD power will be supplied by the load capacitor. Depending on the size of the load capacitor and the DC load of the PD, the PD will not draw any power for a period of time. If this period of time exceeds the IEEE 802.3af 300ms disconnect delay, the PSE will remove power from the PD. For this reason, it is necessary to ensure that inadvertent shutdown cannot occur. Very small output capacitors (10F) will charge very quickly in current limit. The rapidly changing voltage at the output may reduce the current limit temporarily, causing the capacitor to charge at a somewhat reduced rate. Conversely, charging a very large capacitor may cause the current limit to increase slightly. In either case, once the U output voltage reaches its final value, the input current limit will be restored to its nominal value. The load capacitor can store significant energy when fully charged. The design of a PD must ensure that this energy is not inadvertently dissipated in the LTC4267. The polarity-protection diode(s) prevent an accidental short on the cable from causing damage. However, if the VPORTN pin is shorted to VPORTP inside the PD while the capacitor is charged, current will flow through the parasitic body diode of the internal MOSFET and may cause permanent damage to the LTC4267. Maintain Power Signature In an IEEE 802.3af system, the PSE uses the maintain power signature (MPS) to determine if a PD continues to require power. The MPS requires the PD to periodically draw at least 10mA and also have an AC impedance less than 26.25k in parallel with 0.05F. If either the DC current is less than 10mA or the AC impedance is above 26.25k, the PSE may disconnect power. The DC current must be less than 5mA and the AC impedance must be above 2M to guarantee power will be removed. Selecting Feedback Resistor Values The regulated output voltage of the switching regulator is determined by the resistor divider across VOUT (R1 and R2 in Figure 11) and the error amplifier reference voltage VREF. The ratio of R2 to R1 needed to produce the desired voltage can be calculated as: R2 = R1 * (VOUT - VREF)/VREF In an isolated power supply application, VREF is determined by the designer's choice of an external error amplifier. Commercially available error amplifiers or programmable shunt regulators may include an internal reference of 1.25V or 2.5V. Since the LTC4267 internal reference and error amplifier are not used in an isolated design, tie the VFB pin to PGND. In a nonisolated power supply application, the LTC4267 onboard internal reference and error amplifier can be used. The resistor divider output can be tied directly to the VFB pin. The internal reference of the LTC4267 is 0.8V nominal. 4267f W UU 19 LTC4267 APPLICATIO S I FOR ATIO Choose resistance values for R1 and R2 to be as large as possible to minimize any efficiency loss due to the static current drawn from VOUT, but just small enough so that when VOUT is in regulation, the error caused by the nonzero input current from the output of the resistor divider to the error amplifier pin is less that 1%. Error Amplifier and Optoisolator Considerations In an isolated topology, the selection of the external error amplifier depends on the output voltage of the switching regulator. Typical error amplifiers include a voltage reference of either 1.25V or 2.5V. The output of the amplifier and the amplifier upper supply rail are often tied together internally. The supply rail is usually specified with a wide upper voltage range, but it is not allowed to fall below the reference voltage. This can be a problem in an isolated switcher design if the amplifier supply voltage is not properly managed. When the switcher load current decreases and the output voltage rises, the error amplifier responds by pulling more current through the LED. The LED voltage can be as large as 1.5V, and along with RLIM, reduces the supply voltage to the error amplifier. If the error amp does not have enough headroom, the voltage drop across the LED and RLIM may shut the amplifier off momentarily, causing a lock-up condition in the main loop. The switcher will undershoot and not recover until the error amplifier releases its sink current. Care must be taken to select the reference voltage and RLIM value so that the error amplifier always has enough headroom. An alternate solution that avoids these problems is to utilize the LT1431 or LTC4430 where the output of the error amplifier and amplifier supply rail are brought out to separate pins. The PD designer must also select an optoisolator such that its bandwidth is sufficiently wider than the bandwidth of the main control loop. If this step is overlooked, the main control loop may be difficult to stabilize. The output collector resistor of the optoisolator can be selected for an increase in bandwidth at the cost of a reduction in gain of this stage. Output Transformer Design Considerations Since the external feedback resistor divider sets the output voltage, the PD designer has relative freedom in 20 U selecting the transformer turns ratio. The PD designer can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2) which yields more freedom in setting the total turns and mutual inductance and may allow the use of an off the shelf transformer. Transformer leakage inductance on either the primary or secondary causes a voltage spike to occur after the output switch (Q1 in Figure 11) turns off. The input supply voltage plus the secondary-to-primary referred voltage of the flyback pulse (including leakage spike) must not exceed the allowed external MOSFET breakdown rating. This spike is increasingly prominent at higher load currents, where more stored energy must be dissipated. In some cases, a "snubber" circuit will be required to avoid overvoltage breakdown at the MOSFET's drain node. Application Note 19 is a good reference for snubber design. Current Sense Resistor Consideration The external current sense resistor (RSENSE in Figure 11) allows the designer to optimize the current limit behavior for a particular application. As the current sense resistor is varied from several ohms down to tens of milliohms, peak swing current goes from a fraction of an ampere to several amperes. Care must be taken to ensure proper circuit operation, especially for small current sense resistor values. Choose RSENSE such that the switching current exercises the entire range of the ITH/RUN voltage. The nominal voltage range is 0.7V to 1.9V and RSENSE can be determined by experiment. The main loop can be temporarily stabilized by connecting a large capacitor on the power supply. Apply the maximum load current allowable at the power supply output based on the class of the PD. Choose RSENSE such that ITH/RUN approaches 1.9V. Finally, exercise the output load current over the entire operating range and ensure that ITH/RUN voltage remains within the 0.7V to 1.9V range. Layout is critical around the RSENSE resistor. For example, a 0.020 sense resistor, with one milliohm (0.001) of parasitic resistance will cause a 5% reduction in peak switch current. The resistance of printed circuit copper traces cannot necessarily be ignored and good layout techniques are mandatory. 4267f W UU LTC4267 APPLICATIO S I FOR ATIO -48V FROM DATA PAIR + - VPORTP RSTART PVCC PVCC 0.1F 100V VPORTP RCLASS RCLASS SENSE LTC4267 SIGDISA VPORTN ITH/RUN POUT PGND PVCC RC VFB NGATE RSL LPRI PGND CPVCC PGND C1 -48V FROM SPARE PAIR + - VPORTN -48V FROM DATA PAIR + - RSTART R3 0.1F 100V -48V FROM SPARE PAIR + - Figure 11. Typical LTC4267 Application Circuits U ISOLATED DESIGN EXAMPLE T1 D1 VOUT LSEC COUT W UU * * Q1 RLIM RSENSE PGND VPORTP OPTOISOLATOR ERROR AMPLIFIER PGND CC R2 R1 PGND CISO NONISOLATED DESIGN EXAMPLE T1 LBIAS D2 * PGND LPRI PGND CPVCC PGND Q1 RSL RSENSE R2 PGND C1 D1 VOUT LSEC COUT * * PGND PVCC VPORTP RCLASS RCLASS SENSE LTC4267 SIGDISA VPORTN ITH/RUN CC POUT PGND VFB NGATE R1 4267 F11 PGND 4267f 21 LTC4267 APPLICATIO S I FOR ATIO Programmable Slope Compensation The LTC4267 switching regulator injects a ramping current through its SENSE pin into an external slope compensation resistor (RSL in Figure 11). This current ramp starts at zero after the NGATE pin has been high for the LTC4267's minimum duty cycle of 6%. The current rises linearly towards a peak of 5A at the maximum duty cycle of 80%, shutting off once the NGATE pin goes low. A series resistor (RSL) connecting the SENSE pin to the current sense resistor (RSENSE) develops a ramping voltage drop. From the perspective of the LTC4267 SENSE pin, this ramping voltage adds to the voltage across the sense resistor, effectively reducing the current comparator threshold in proportion to duty cycle. This stabilizes the control loop against subharmonic oscillation. The amount of reduction in the current comparator threshold (VSENSE) can be calculated using the following equation: VSENSE = 5A * RSL * [(Duty Cycle - 6%)/74%] Note: The LTC4267 enforces 6% < Duty Cycle < 80%. Designs not needing slope compensation may replace RSL with a short-circuit. Applications Employing a Third Transformer Winding A standard operating topology may employ a third winding on the transformer's primary side that provides power to the LTC4267 switching regulator via its PVCC pin (Figure 11). However, this arrangement is not inherently self-starting. Start-up is usually implemented by the use of an external "trickle-charge" resistor (RSTART) in conjunction with the internal wide hysteresis undervoltage lockout circuit that monitors the PVCC pin voltage. RSTART is connected to VPORTP and supplies a current, typically 100A, to charge CPVCC. After some time, the voltage on CPVCC reaches the PVCC turn-on threshold. The LTC4267 switching regulator then turns on abruptly and draws its normal supply current. The NGATE pin begins switching and the external MOSFET (Q1) begins to deliver power. The voltage on CPVCC begins to decline as the switching regulator draws its normal supply current, which exceeds the delivery from RSTART. After some time, typically tens of milliseconds, the output voltage approaches the desired value. By this time, the third transformer winding 22 U is providing virtually all the supply current required by the LTC4267 switching regulator. One potential design pitfall is under-sizing the value of capacitor CPVCC. In this case, the normal supply current drawn through PVCC will discharge CPVCC rapidly before the third winding drive becomes effective. Depending on the particular situation, this may result in either several off-on cycles before proper operation is reached or permanent relaxation oscillation at the PVCC node. Resistor RSTART should be selected to yield a worst-case minimum charging current greater that the maximum rated LTC4267 start-up current to ensure there is enough current to charge CPVCC to the PVCC turn-on threshold. RSTART should also be selected large enough to yield a worst-case maximum charging current less than the minimum-rated PVCC supply current, so that in operation, most of the PVCC current is delivered through the third winding. This results in the highest possible efficiency. Capacitor CPVCC should then be made large enough to avoid the relaxation oscillation behavior described previously. This is difficult to determine theoretically as it depends on the particulars of the secondary circuit and load behavior. Empirical testing is recommended. The third transformer winding should be designed so that its output voltage, after accounting for the forward diode voltage drop, exceeds the maximum PVCC turn-off threshold. Also, the third winding's nominal output voltage should be at least 0.5V below the minimum rated PVCC clamp voltage to avoid running up against the LTC4267 shunt regulator, needlessly wasting power. PVCC Shunt Regulator In applications including a third transformer winding, the internal PVCC shunt regulator serves to protect the LTC4267 switching regulator from overvoltage transients as the third winding is powering up. If a third transformer winding is undesirable or unavailable, the shunt regulator allows the LTC4267 switching regulator to be powered through a single dropping resistor from VPORTP as shown in Figure 12. This simplicity comes at the expense of reduced efficiency due to static power dissipation in the RSTART dropping resistor. 4267f W UU LTC4267 APPLICATIO S I FOR ATIO The shunt regulator can sink up to 5mA through the PVCC pin to PGND. The values of RSTART and CPVCC must be selected for the application to withstand the worst-case load conditions and drop on PVCC, ensuring that the PVCC turn-off threshold is not reached. CPVCC should be sized sufficiently to handle the switching current needed to drive NGATE while maintaining minimum switching voltage. + VPORTP - 48 FROM PSE RSTART PVCC LTC4267 PGND CPVCC - VPORTN POUT PGND 4267 F14 Figure 12. Powering the LTC4267 Switching Regulator via the Shunt Regulator External Preregulator The circuit in Figure 13 shows a third way to power the LTC4267 switching regulator circuit. An external series preregulator consists of a series pass transistor Q1, zener diode D1, and a bias resistor RB. The preregulator holds PVCC at 7.6V nominal, well above the maximum rated PVCC turn-off threshold of 6.8V. Resistor RSTART momentarily charges the PVCC node up to the PVCC turn-on threshold, enabling the switching regulator. The voltage on CPVCC begins to decline as the switching regulator draws its normal supply current, which exceeds the delivery of RSTART. After some time, the output voltage approaches the desired value. By this time, the pass transistor Q1 catches the declining voltage on the PVCC pin, and provides virtually all the supply current required by the LTC4267 switching regulator. CPVCC should be sized sufficiently to handle the switching current needed to drive NGATE while maintaining minimum switching voltage. The external preregulator has improved efficiency over the simple resistor-shunt regulator method mentioned previously. RB can be selected so that it provides a small current necessary to maintain the zener diode voltage and the maximum possible base current Q1 will encounter. The U actual current needed to power the LTC4267 switching regulator goes through Q1 and PVCC sources current on an "as-needed" basis. The static current is then limited only to the current through RB and D1. + RB VPORTP -48 FROM PSE PVCC LTC4267 PGND D1 8.2V PGND CPVCC PGND Q1 RSTART W UU - VPORTN POUT PGND 4267 F15 Figure 13. Powering the LTC4267 Switching Regulator with an External Preregulator Compensating the Main Loop In an isolated topology, the compensation point is typically chosen by the components configured around the external error amplifier. Shown in Figure 14, a series RC network is connected from the compare voltage of the error amplifier to the error amplifier output. In PD designs where transient load response is not critical, replace RZ with a short. The product of R2 and CC should be sufficiently large to ensure stability. When fast settling transient response is critical, introduce a zero set by RZCC. The PD designer must ensure that the faster settling response of the output voltage does not compromise loop stability. In a nonisolated design, the LTC4267 incorporates an internal error amplifier where the ITH/RUN pin serves as a compensation point. In a similar manner, a series RC network can be connected from ITH/RUN to PGND as shown in Figure 15. CC and RZ are chosen for optimum load and line transient response. TO OPTOISOLATOR RZ CC VOUT R2 R1 4267 F14 Figure 14. Main Loop Compensation for an Isolated Design 4267f 23 LTC4267 APPLICATIO S I FOR ATIO LTC4267 ITH/RUN CC PGND RZ 4267 F15 Figure 15. Main Loop Compensation for a Nonisolated Design Selecting the Switching Transistor With the N-channel power MOSFET driving the primary of the transformer, the inductance will cause the drain of the MOSFET to traverse twice the voltage across VPORTP and PGND. The LTC4267 operates with a maximum supply of - 57V; thus the MOSFET must be rated to handle 114V or more with sufficient design margin. Typical transistors have 150V ratings while some manufacturers have developed 120V rated MOSFETs specifically for Power-over-Ethernet applications. The NGATE pin of the LTC4267 drives the gate of the N-channel MOSFET. NGATE will traverse a rail-to-rail voltage from PGND to PVCC. The designer must ensure the MOSFET provides a low "ON" resistance when switched to PVCC as well as ensure the gate of the MOSFET can handle the PVCC supply voltage. For high efficiency applications, select an N-channel MOSFET with low total gate charge. The lower total gate charge improves the efficiency of the NGATE drive circuit and minimizes the switching current needed to charge and discharge the gate. Auxiliary Power Source In some applications, it may be desirable to power the PD from an auxiliary power source such as a wall transformer. The auxiliary power can be injected into the PD at several locations and various trade-offs exist. Power can be injected at the 3.3V or 5V output of the isolated power supply with the use of a diode ORing circuit. This method accesses the internal circuits of the PD after the isolation barrier and therefore meets the 802.3af isolation safety requirements for the wall transformer jack on the PD. Power can also be injected into the PD interface portion 24 U of the LTC4267. In this case, it is necessary to ensure the user cannot access the terminals of the wall transformer jack on the PD since this would compromise the 802.3af isolation safety requirements. Figure 16 demonstrates three methods of diode ORing external power into a PD. Option 1 inserts power before the LTC4267 interface controller while options 2 and 3 bypass the LTC4267 interface controller section and power the switching regulator directly. If power is inserted before the LTC4267 interface controller, it is necessary for the wall transformer to exceed the LTC4267 UVLO turn-on requirement and include a transient voltage suppressor (TVS) to limit the maximum voltage to 57V. This option provides input current limit for the transformer, provides a valid power good signal, and simplifies power priority issues. As long as the wall transformer applies power to the PD before the PSE, it will take priority and the PSE will not power up the PD because the wall power will corrupt the 25k signature. If the PSE is already powering the PD, the wall transformer power will be in parallel with the PSE. In this case, priority will be given to the higher supply voltage. If the wall transformer voltage is higher, the PSE should remove the line voltage since no current will be drawn from the PSE. On the other hand, if the wall transformer voltage is lower, the PSE will continue to supply power to the PD and the wall transformer will not be used. Proper operation should occur in either scenario. If auxiliary power is applied directly to the LTC4267 switching regulator (bypassing the LTC4267 PD interface), a different set of tradeoffs arise. In the configuration shown in option 2, the wall transformer does not need to exceed the LTC4267 turn-on UVLO requirement; however, it is necessary to include diode D9 to prevent the transformer from applying power to the LTC4267 interface controller. The transformer voltage requirement will be governed by the needs of the onboard switching regulator. However, power priority issues require more intervention. If the wall transformer voltage is below the PSE voltage, then priority will be given to the PSE power. The LTC4267 interface controller will draw power from the PSE while the transformer will sit unused. This configuration is not a problem in a PoE system. On the other hand, if the wall 4267f W UU LTC4267 APPLICATIO S I FOR ATIO RJ45 1 TX+ - OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267 PD T1 2 3 TX RX+ RX- TO PHY 6 4 5 7 8 SPARE+ SPARE- ISOLATED WALL 38V TO 57V TRANSFORMER + - OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267 PD WITH SIGNATURE DISABLED RJ45 1 TX+ TX- RX+ RX- TO PHY T1 2 3 6 4 5 7 8 SPARE+ SPARE- ISOLATED WALL TRANSFORMER + - OPTION 3: AUXILIARY POWER APPLIED TO LTC4267 PD AND SWITCHING REGULATOR RJ45 1 TX+ TX- RX+ RX- TO PHY T1 2 3 6 4 5 7 8 SPARE+ SPARE- ISOLATED WALL TRANSFORMER + 38V TO 57V - Figure 16. Auxiliary Power Source for PD 4267f U ~ BR1 HD01 W UU + D3 SMAJ58A TVS C14 0.1F 100V C1 VPORTP RSTART ~ - ~ BR2 HD01 + PVCC LTC4267 PGND CPVCC ~ - D8 S1B VPORTN POUT PGND ~ BR1 HD01 + D3 SMAJ58A TVS C14 0.1F 100V BSS63 VPORTP 100k RSTART ~ - SIGDISA PVCC LTC4267 PGND C1 100k ~ BR2 HD01 + CPVCC ~ - VPORTN POUT D9 S1B PGND D10 S1B ~ BR1 HD01 + D3 SMAJ58A TVS C14 0.1F 100V C1 VPORTP RSTART ~ - PVCC LTC4267 PGND ~ BR2 HD01 + CPVCC ~ - VPORTN POUT PGND D10 S1B 4267 F16 25 LTC4267 APPLICATIO S I FOR ATIO transformer voltage is higher than the PSE voltage, the LTC4267 switching regulator will draw power from the transformer. In this situation, it is necessary to address the issue of power cycling that may occur if a PSE is present. The PSE will detect the PD and apply power. If the switcher is being powered by the wall transformer, then the PD will not meet the minimum load requirement and the PSE will subsequently remove power. The PSE will again detect the PD and power cycling will start. With a transformer voltage above the PSE voltage, it is necessary to either disable the signature, as shown in option 2, or install a minimum load on the output of the LTC4267 interface to prevent power cycling. The third option also applies power directly to the LTC4267 switching regulator, bypassing the LTC4267 interface controller and omitting diode D9. With the diode omitted, the transformer voltage is applied to the LTC4267 interface controller in addition to the switching regulator. For this reason, it is necessary to ensure that the transformer maintain the voltage between 38V and 57V to keep the LTC4267 interface controller in its normal operating range. The third option has the advantage of automatically disabling the 25k signature resistor when the external voltage exceeds the PSE voltage. Power-Up Sequencing the LTC4267 The LTC4267 consists of two functional cells, the PD interface and the switching regulator, and the power up sequencing of these two cells must be carefully considered. The PD designer should ensure that the switching regulator does not begin operation until the interface has completed charging up the load capacitor. This will ensure that the switcher load current does not compete with the load capacitor charging current provided by the PD interface current limit circuit. Overlooking this consideration may result in slow power supply ramp up, power-up oscillation, and possibly thermal shutdown. The LTC4267 includes a power good signal in the PD interface that can be used to indicate to the switching regulator that the load capacitor is fully charged and ready to handle the switcher load. Figure 7 shows two examples of ways the PWRGD signal can be used to control the switching regulator. The first example employs an N-channel MOSFET 26 U to drive the ITH/RUN port below the shutdown threshold (typically 0.28V). The second example drives PVCC below the PVCC turn-off threshold. Employing the second example has the added advantage of adding delay to the switching regulator start-up beyond the time the power good signal becomes active. The second example ensures additional timing margin at start-up without the need for added delay components. In applications where it is not desirable to utilize the power good signal, sufficient timing margin can be achieved with RSTART and CPVCC. RSTART and CPVCC should be set to a delay of two to three times longer than the duration needed to charge up C1. Layout Considerations for the LTC4267 The most critical layout considerations for the LTC4267 are the placement of the supporting external components associated with the switching regulator. Efficiency, stability, and load transient response can deteriorate without good layout practices around critical components. For the LTC4267 switching regulator, the current loop through C1, T1 primary, Q1, and RSENSE must be given careful layout attention. (Refer to Figure 11.) Because of the high switching current circulating in this loop, these components should be placed in close proximity to each other. In addition, wide copper traces or copper planes should be used between these components. If vias are necessary to complete the connectivity of this loop, placing multiple vias lined perpendicular to the flow of current is essential for minimizing parasitic resistance and reducing current density. Since the switching frequency and the power levels are substantial, shielding and high frequency layout techniques should be employed. A low current, low impedance alternate connection should be employed between the PGND pins of the LTC4267 and the PGND side of RSENSE, away from the high current loop. This Kelvin sensing will ensure an accurate representation of the sense voltage is measured by the LTC4267. The placement of the feedback resistors R1 and R2 as well as the compensation capacitor CC is very important in the accuracy of the output voltage, the stability of the main control loop, and the load transient response. In an isolated design application, R1, R2, and CC should be placed as close as possible to the error amplifier's input 4267f W UU LTC4267 APPLICATIO S I FOR ATIO with minimum trace lengths and minimum capacitance. In a nonisolated application, R1, and R2 should be placed as close as possible to the VFB pin of the LTC4267 and CC should be placed close to the ITH/RUN pin of the LTC4267. In essence, a tight overall layout of the high current loop and careful attention to current density will ensure successful operation of the LTC4267 in a PD. The PD interface section of the LTC4267 is relatively immune to layout problems. Excessive parasitic capacitance on the RCLASS pin should be avoided. If using the DHC package, include an electrically isolated heat sink to which the exposed pad on the bottom of the package can be soldered. For optimum thermal performance, make the heat sink as large as possible. The SIGDISA pin is adjacent to the VPORTP pin and any coupling, whether resistive U or capacitive may inadvertently disable the signature resistance. To ensure consistent behavior, the SIGDISA pin should be electrically connected and not left floating. Voltages in a PD can be as large as -57V, so high voltage layout techniques should be employed. Electro Static Discharge and Surge Protection The LTC4267 is specified to operate with an absolute maximum voltage of -100V and is designed to tolerate brief overvoltage events. However, the pins that interface to the outside world (primarily VPORTN and VPORTP) can routinely see peak voltages in excess of 10kV. To protect the LTC4267, it is highly recommended that a transient voltage suppressor be installed between the diode bridge and the LTC4267 (D3 in Figure 2). 4267f W UU 27 LTC4267 TYPICAL APPLICATIO S A High-Efficiency Class 3 PD with 3.3V Isolated Power Supply 10 PULSE PA1136 5F* MIN 470pF 220k 220k 330 510 MMTBA42 MMSD4148 -48V FROM DATA PAIR SMAJ58A 0.1F -48V FROM SPARE PAIR RCLASS 45.3 1% SIGDISA VPORTN *1F CERAMIC + 4.7F TANTALUM **100F CERAMIC + 470F TANTALUM POUT PWRGD 10k VFB PGND MMSD4148 TLV431 60.4k 1% VPORTP LTC4267 B1100 (8 PLACES) NGATE 10k SENSE ITH/RUN PVCC 100k 0.068 1% PVCC 6.8k 33nF 100k 1% 500 Si3440 PVCC 4.7F 9.1V BAS516 PVCC BAS516 150pF * BAS516 2N7002 PS2911 2200pF "Y" CAP 250VAC 28 * * U SBM1040 3.3V 2.6A 570F** CHASSIS 4267 TA02 4267f LTC4267 TYPICAL APPLICATIO S A Class 3 PD with 5V Nonisolated Power Supply COILTRONICS CTX-02-15242 5F* MIN 220k 100k MMBTA42 BAS516 VPORTP LTC4267 SMAJ58A 0.1F NGATE PWRGD 10k -48V FROM SPARE PAIR RCLASS 45.3 1% SIGDISA VPORTN *1F CERAMIC + 4.7F TANTALUM ** THREE 100F CERAMICS POUT PGND SENSE VFB ITH/RUN 22nF 27k 8.06k 1% 0.04 1% 42.2k 1% 4267 TA03 -48V FROM DATA PAIR + HD01 PVCC - + HD01 - U 5V 1.8A 300F* UPS840 * 9.1V * 1F FDC2512 150pF 200V 220 4267f 29 LTC4267 PACKAGE DESCRIPTIO U DHC Package 16-Lead Plastic DFN (5mm x 3mm) (Reference LTC DWG # 05-08-1706) 9 16 (DHC16) DFN 1103 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 8 1 NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4267f 30 LTC4267 PACKAGE DESCRIPTIO U GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) 0 - 8 TYP .254 MIN RECOMMENDED SOLDER PAD LAYOUT 23 4 56 7 8 .004 - .0098 (0.102 - 0.249) .0532 - .0688 (1.35 - 1.75) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 4267f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC4267 RELATED PARTS PART NUMBER LTC1737 LTC1871 LTC3803 LTC4257 LTC4257-1 LTC4258 LTC4259A DESCRIPTION High Power Isolated Flyback Controller Wide Input Range, No RSENSETM Current Mode Flyback, Boost and SEPIC Controller Current Mode Flyback DC/DC Controller in ThinSOTTM IEEE 802.3af PD Interface Controller IEEE 802.3af PD Interface Controller with Dual Current Limit Quad IEEE 802.3af Power over Ethernet Controller Quad IEEE 802.3af Power over Ethernet Controller COMMENTS Sense Output Voltage Directly from Primary Side Winding Adjustable Switching Frequency, Programmable Undervoltage Lockout, (R) Optional Burst Mode Operation at Light Load 200kHz Constant Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications 100V 400mA Internal Switch, Programmable Classification 100V 400mA Internal Switch, Programmable Classification, Supports Legacy Applications DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2CTM Control AC or DC Disconnect IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2CTM Control Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V. 4267f 32 Linear Technology Corporation (408) 432-1900 FAX: (408) 434-0507 LT/TP 1004 1K * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2004 |
Price & Availability of LTC4267
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |